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march 2007 hys72t32000hr?[2.5/3/3s/3.7/5]?a HYS72T64001HR?[2.5/3/3s/3.7/5]?a hys72t64020hr?[2.5/3/3s/3.7/5]?a 240-pin registered ddr2 sdram modules ddr2 sdram rdimm sdram rohs compliant internet data sheet rev. 1.21
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 09152006-j5fk-c565 hys72t32000hr?[2.5/3/3s/3.7/5]?a, HYS72T64001HR?[2.5 /3/3s/3.7/5]?a, hys72t64020hr?[2.5/3/3s/3.7/5]?a revision history: 2007-03, rev. 1.21 page subjects (major chan ges since last revision) all qimonda update all adapted internet edition previous revision: 2005-09, rev. 1.2 chapter 4 spd codes update: byte 49 bit 0 = 1 (hight_srfentry) for all product types chapter 5 package outlines updated previous revision: 2005-06, rev. 1.1
internet data sheet rev. 1.21, 2007-03 3 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 1overview this chapter gives an overview of t he 240-pin registered ddr2 sdram modules product family and describes its main characteristics. 1.1 features ? 240-pin pc2-6400, pc2-5300, pc2-4200 and pc2-3200 ddr2 sdram memory modules for pc, workstation and server main memory applications ? one rank 32m x 72, 64m x 72 and two ranks 64m 72 module organization and 32m 8, 64m 4 chip organization ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? all speed grades faster than ddr2?400 comply with ddr2?400 timing specifications ? built with 256-mbit ddr2 sdrams in p-tfbga-60 chipsize packages. ? programmable cas latencies (3, 4, 5 & 6), burst length (4 & 8) and burst type ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? rdimm dimensions (nominal): 30 mm high, 133.35 mm wide ? based on standard reference la youts raw card ?a-f?, ?b- g? & ?c-h? ? rohs compliant products 1) table 1 performance for ?2.5 & ?3 (s) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?2.5 ?3 ?3s unit speed grade pc2?6400 6?6?6 pc2?5300 4?4?4 pc2?5300 5?5?5 ? max. clock frequency @cl6 f ck6 400 333 333 @cl5 f ck5 333 333 333 mhz @cl4 f ck4 266 333 266 mhz @cl3 f ck3 200 200 200 mhz min. ras-cas-delay t rcd 15 12 15 ns min. row precharge time t rp 15 12 15 ns min. row active time t ras 45 45 45 ns min. row cycle time t rc 60 57 60 ns
internet data sheet rev. 1.21, 2007-03 4 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 2 performance for ddr2 -533 and ddr2-400 product type speed code ?3.7 ?5 units speed grade pc2?4200 4?4?4 pc2?3200 3?3?3 ? max. clock frequency @cl5 f ck5 266 200 mhz @cl4 f ck4 266 200 mhz @cl3 f ck3 200 200 mhz min. ras-cas-delay t rcd 15 15 ns min. row precharge time t rp 15 15 ns min. row active time t ras 45 40 ns min. row cycle time t rc 60 55 ns
internet data sheet rev. 1.21, 2007-03 5 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 1.2 description the qimonda hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a module family are registered dimm modules ?rdimms? with 30 mm height based on ddr2 technology. dimms are available as ecc modules in 32m x 72 (256 mbyte) and 64m x 72 (512 mbyte) organization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 256-mbit double-data- rate-two (ddr2) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feat ure serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and are write-protected; the second 128 bytes are available to the customer. table 3 ordering information for rohs compliant products product type 1) 1) all part numbers end with a place code, des ignating the silicon di e revision. example: hys72t32000hr?5?a, indicating rev. ?a? dies are used for ddr2 sdram components. for all qimonda ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200r?444?11?f0?, where 4200r means registered dimm modules with 4.26 gb/sec module bandw idth and ?444-11? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.1 and produced on the raw card ?f? description sdram technology pc2-6400 hys72t32000hr?2.5?a 256 mb 1r 8 pc2?6400r?666?12?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HR?2.5?a 512 mb 1r 4 pc2?6400r?666?12?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hr?2.5?a 512 mb 2r 8 pc2?6400r?666?12?g0 2 rank, ecc 256 mbit ( 8) pc2-5300 hys72t32000hr?3?a 256 mb 1r 8 pc2?5300r?444?12?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HR?3?a 512 mb 1r 4 pc2?5300r?444?12?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hr?3?a 512 mb 2r 8 pc2?5300r?444?12?g0 2 rank, ecc 256 mbit ( 8) hys72t32000hr?3s?a 256 mb 1r 8 pc2?5300r?555?12?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HR?3s?a 512 mb 1r 4 pc2?5300r?555?12?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hr?3s?a 512 mb 2r 8 pc2?5300r?555?12?g0 2 rank, ecc 256 mbit ( 8) pc2?4200 hys72t32000hr?3.7?a 256 mb 1r 8 pc2?4200r?444?11?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HR?3.7?a 512 mb 1r 4 pc2?4200r?444?11?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hr?3.7?a 512 mb 2r 8 pc2?4200r?444?11?g0 2 rank, ecc 256 mbit ( 8) pc2-3200 hys72t32000hr?5?a 256 mb 1r 8 pc2?3200r?333?11?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HR?5?a 512 mb 1r 4 pc2?3200r?333?11?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hr?5?a 512 mb 2r 8 pc2?3200r?333?11?g0 2 rank, ecc 256 mbit ( 8)
internet data sheet rev. 1.21, 2007-03 6 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 4 address format table 5 components on modules dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 256 mb 32m 72 1 ecc 9 13/2/10 a-f 512 mb 64m 72 1 ecc 18 13/2/11 c-h 512 mb 64m 72 2 ecc 18 13/2/10 b-g product type 1) 1) green product dram components 1) dram density dram organization note 2) 2) for a detailed description of all avail able functions of the dram components on these modules see the component data sheet. hys72t32000hr hyb18t256800af 256 mbit 32m 8 ? HYS72T64001HR hyb18t256400af 256 mbit 64m 4 ? hys72t64020hr hyb18t256800af 256 mbit 32m 8 ?
internet data sheet rev. 1.21, 2007-03 7 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 2 pin configuration the pin configuration of the registered ddr2 sdram dimm is listed by function in table 6 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 7 and table 8 respectively. the pin numbering is depicted in figure 1 . table 6 pin configuration of rdimm ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, comple mentary clock signal ck0 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select rank 1:0 note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module 192 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) 74 cas isstl 73 we isstl 18 reset icmos register reset address signals 71 ba0 i sstl bank address bus 1:0 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 greater than 512mb ddr2 sdrams nc i sstl not connected less than 1gb ddr2 sdrams
internet data sheet rev. 1.21, 2007-03 8 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 nc nc ? not connected note: non ca parity modules based on 256 mbit component 174 a14 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. 173 a15 i sstl address signal 14 note: ca parity module nc nc ? not connected note: non ca parity module. less than 1 gbit per dram die. ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 9 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules data signals 3 dq0 i/o sstl data bus 63:0 data input/output pins 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 10 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 206 dq39 i/o sstl data bus 63:0 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 check bit input / output pins note: nc on non-ecc module 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl 161 cb4 i/o sstl 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 11 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules data strobe bus 7 dqs0 i/o sstl data strobes 17:0 6 dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 125 dqs9 i/o sstl 126 dqs9 i/o sstl 134 dqs10 i/o sstl 135 dqs10 i/o sstl 146 dqs11 i/o sstl 147 dqs11 i/o sstl 155 dqs12 i/o sstl 156 dqs12 i/o sstl 202 dqs13 i/o sstl 203 dqs13 i/o sstl 211 dqs14 i/o sstl 212 dqs14 i/o sstl 223 dqs15 i/o sstl 224 dqs15 i/o sstl 232 dqs16 i/o sstl 233 dqs16 i/o sstl 164 dqs17 i/o sstl 165 dqs17 i/o sstl ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 12 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules data mask 125 dm0 i sstl data masks 8:0 note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 101 sa2 i cmos parity 55 err_out ocmos parity bits par_in i cmos power supplies 1 v ref ai ? i/o reference voltage 238 v ddspd pwr ? eeprom power supply 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194 v ddq pwr ? i/o driver power supply 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197 v dd pwr ? power supply 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 13 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 7 abbreviations for buffer type table 8 abbreviations for pin type other pins 19, 55, 68, 102, 137, 138, 173, 220, 221 nc nc ? not connected 195 odt0 i sstl on-die termination control 1:0 note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or. abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected ball no. name pin type buffer type function
internet data sheet rev. 1.21, 2007-03 14 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules figure 1 pin configuration for rdimm (240 pins) 0337 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 95() '4 9 66 '46 '4 9 66 '4 '46 9 66 1& 9 66 '4 '46 9 66 '4 '4 9 66 '46 5(6(7 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 &% 9 66 '46 &% 9 66 &.( 1&%$ 9 ''4 $ $ 9 ''4 9 '' 9 66 1& $$3 9 ''4 &$6 1&6 9 ''4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 1& '46 9 66 '4 '4 9 66 '46 '4 9 66 6&/ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 &% '46 9 66 &% 9 ''4 9 '' 1& $ 9 '' $ $ 9 66 9 '' 9 '' %$ :( 9 ''4 1&2'7 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 6$ 9 66 '46 '4 9 66 '4 '46 9 66 '4 6'$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 1& 9 66 '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 1& '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 &% '0'46 9 66 &% 9 ''4 9 '' 1&$ $ 9 '' $ $ 9 '' &. $ %$ 5$6 9 ''4 1&$ 9 66 '4 '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 '4 1& 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 9''63' 6$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 &% 9 66 1&'46 &% 9 66 1&&.( 1&$ 9 ''4 $ $ 9 ''4 $ &. 9 '' 9 '' 9 ''4 6 2'7 9 '' '4 9 66 1&'46 '4 9 66 '4 '0'46 9 66 '4 '4 9 66 1& '0'46 9 66 '4 '4 9 66 1&'46 '4 9 66 6$ )52176,'( %$&.6,'(
internet data sheet rev. 1.21, 2007-03 15 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3 electrical characteristics this chapter lists the el ectrical characteristics. 3.1 absolute maximum ratings caution is needed not to exceed absolute maximum ratings of the dram device listed in table 9 at any time. table 9 absolute maximum ratings attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. table 10 dram component operating temperature range symbol parameter rating unit note min. max. v dd voltage on v dd pin relative to v ss ?1.0 +2.3 v 1) 1) when v dd and v ddq and v ddl are less than 500 mv; v ref may be equal to or less than 300 mv. v ddq voltage on v ddq pin relative to v ss ?0.5 +2.3 v 1)2) v ddl voltage on v ddl pin relative to v ss ?0.5 +2.3 v 1)2) v in , v out voltage on any pin relative to v ss ?0.5 +2.3 v 1) t stg storage temperature ?55 +100 c 1)2) 2) storage temperature is the case surface temperature on the center/top side of the dram. symbol parameter rating unit note min. max. t oper operating temperature 0 95 c 1)2)3)4) 1) operating temperature is the case surface te mperature on the center / top side of the dram. 2) the operating temperature range are the temperatures where all dram specification will be supported. during operation, the dr am case temperature must be maintained between 0 - 95 c under all other specification parameters. 3) above 85 c the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c tcase tem perature range, the high temperature self refresh has to be enable d by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50 %
internet data sheet rev. 1.21, 2007-03 16 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3.2 dc operating conditions this chapter contains the dc operating conditions tables. table 11 operating conditions table 12 supply voltage levels an d dc operating conditions parameter symbol values unit note min. max. operating temperature (ambient) t opr 0+65 c? dram case temperature t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. 2) within the dram component case temperature range all dram specificat ions will be supported 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s 4) when operating this product in the 85 c to 95 c t case temperature range, the high temperature self refresh has to be enabled by setting emr(2) bit a7 to ?1?. when the high temperatur e self refresh is enabled there is an increase of i dd6 by approximately 50 %. storage temperature t stg ? 50 +100 c? barometric pressure (operating & storage) p bar +69 +105 kpa 5) 5) up to 3000 m. operating humidity (relative) h opr 10 90 % ? parameter symbol values unit note min. typ. max. device supply voltage v dd 1.7 1.8 1.9 v ? output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise in v ddq . spd supply voltage v ddspd 1.7 ? 3.6 v ? dc input logic high v ih(dc) v ref + 0.125 ? v ddq +0.3 v ? dc input logic low v il (dc ) ? 0.30 ? v ref ? 0.125 v ? in / output leakage current i l ? 5 ? 5 a 3) 3) input voltage for any connector pin under test of 0 v v in v ddq + 0.3 v; all other pins at 0 v. current is per pin
internet data sheet rev. 1.21, 2007-03 17 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3.3 ac characteristics this chapter describes the ac characteristics. 3.3.1 speed grades definitions this chapter contains the speed grades definitions tables. table 13 speed grade definition speed bins for ddr2?800e speed grade ddr2?800e unit note qag sort name ?2.5 cas-rcd-rp latencies 6?6?6 t ck parameter symbol min. max. ? clock frequency @ cl = 3 t ck 58 ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 ns 1)2)3)4) @ cl = 5 t ck 38 ns 1)2)3)4) @ cl = 6 t ck 2.5 8 ns 1)2)3)4) row active time t ras 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 devic e can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? ns 1)2)3)4) row precharge time t rp 15 ? ns 1)2)3)4)
internet data sheet rev. 1.21, 2007-03 18 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 14 speed grade definition speed bins for ddr2?667 table 15 speed grade definition speed bi ns for ddr2-533 and ddr2-400 speed grade ddr2?667c ddr2?667d unit note qag sort name ?3 ?3s cas-rcd-rp latencies 4?4?4 5?5?5 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 383.758ns 1)2)3)4) @ cl = 5 t ck 3838ns 1)2)3)4) row active time t ras 45 70000 45 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 dev ice can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 57 ? 60 ? ns 1)2)3)4) ras-cas-delay t rcd 12 ? 15 ? ns 1)2)3)4) row precharge time t rp 12 ? 15 ? ns 1)2)3)4) speed grade ddr2?533c ddr2?400b unit note qag sort name ?3.7 ?5 cas-rcd-rp latencies 4?4?4 3?3?3 t ck parameter symbol min. max. min. max. ? clock frequency @ cl = 3 t ck 5858ns 1)2)3)4) 1) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. timings are further guaranteed for normal ocd drive strength (emrs(1) a1 = 0) . 2) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode 3) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 4) the output timing reference voltage level is v tt . @ cl = 4 t ck 3.75 8 5 8 ns 1)2)3)4) @ cl = 5 t ck 3.75 8 5 8 ns 1)2)3)4) row active time t ras 45 70000 40 70000 ns 1)2)3)4)5) 5) t ras.max is calculated from the maximum amount of time a ddr2 dev ice can operate without a refresh command which is equal to 9 x t refi . row cycle time t rc 60 ? 55 ? ns 1)2)3)4) ras-cas-delay t rcd 15 ? 15 ? ns 1)2)3)4) row precharge time t rp 15 ? 15 ? ns 1)2)3)4)
internet data sheet rev. 1.21, 2007-03 19 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3.3.2 ac timing parameters this chapter contains t he ac timing parameters. table 16 timing parameter by speed grade - ddr2?800 parameter symbol ddr2?800 unit note 1)2)3)4)5)6)7) 8) min. max. dq output access time from ck / ck t ac ?400 +400 ps 9) dqs output access time from ck / ck t dqsck ?350 +350 ps 9) average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 2500 8000 ps 10)11) dq and dm input setup time t ds.base 50 ? ps 12)13)14) dq and dm input hold time t dh.base 125 ? ps 12)13)15) control & address input pulse width for each input t ipw 0.6 ? t ck.avg ? dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg ? data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)16) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)16) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)16) dqs-dq skew for dqs & associated dq signals t dqsq ? 200 ps 17) ck half pulse width t hp min ( t ch.abs , t cl.abs ) __ ps 18) dq hold skew factor t qhs ? 300 ps 19) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 20) write command to dqs associated clock edges wl rl ? 1 nck ? dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 21) dqs input high pulse width t dqsh 0.35 ? t ck.avg ? dqs input low pulse width t dqsl 0.35 ? t ck.avg ? dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 21) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 21) write postamble t wpst 0.4 0.6 t ck.avg ? write preamble t wpre 0.35 ? t ck.avg ? address and control input setup time t ls.base 175 ? ps 22)23) address and control input hold time t lh.base 250 ? ps 23)24) read preamble t rpre 0.9 1.1 t ck.avg 25)26) read postamble t rpst 0.4 0.6 t ck.avg 25)27) active to precharge command t ras 45 70000 ns 28) active to active command period for 1kb page size products t rrd 7.5 ? ns 28) active to active command period for 2kb page size products t rrd 10 ? ns 28)
internet data sheet rev. 1.21, 2007-03 20 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules four activate window for 1kb page size products t faw 35 ? ns 28) four activate window for 2kb page size products t faw 45 ? ns 28) cas to cas command delay t ccd 2?nck? write recovery time t wr 15 ? ns 28) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 29)30) internal write to read command delay t wtr 7.5 ? ns 28)31) internal read to precharge command delay t rtp 7.5 ? ns 28) exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 28) exit self-refresh to read command t xsrd 200 ? nck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck? exit power down to read command t xard 2?nck? exit active power-down mode to read command (slow exit, lower power) t xards 8 ? al ? nck ? cke minimum pulse width ( high and low pulse width) t cke 3?nck 32) odt turn-on delay t aond 22nck? odt turn-on t aon t ac.min t ac.max +0.7 ns 9)33) odt turn-on (power down mode) t aonpd t ac.min +2 2 x t ck.avg + t ac.max +1 ns ? odt turn-off delay t aofd 2.5 2.5 nck ? odt turn-off t aof t ac.min t ac.max +0.6 ns 34)35) odt turn-off (power down mode) t aofpd t ac.min + 2 2.5 x t ck.avg + t ac.max +1 ns ? odt to power down entry latency t anpd 3??nck? odt to power down exit latency t axpd 8nck? mode register set command cycle time t mrd 2?nck? mrs command to odt update delay t mod 012ns 28) ocd drive mode output delay t oit 012ns 28) minimum time clocks remain on after cke asynchronously drops low t delay t ls + t ck .avg + t lh ?? ns ? 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . parameter symbol ddr2?800 unit note 1)2)3)4)5)6)7) 8) min. max.
internet data sheet rev. 1.21, 2007-03 21 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are referr ed to as 'input clock jitter s pec parameters' and these parame ters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per their average values, howe ver it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations). 12) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal applied to the devic e under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 2 . 13) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 14) these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 2 . 16) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 17) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 18) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. 19) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 20) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 21) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 22) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 3 . 23) these parameters are measured from a command/address signal (c ke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal cr ossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 24) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 3 . 25) t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 1 shows a method to calculate these points when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 26) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!).
internet data sheet rev. 1.21, 2007-03 22 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 17 timing parameter by speed grade - ddr2?667 27) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 28) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are me t. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 29) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 31) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 32) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clo cks of registration. thus, after any cke tr ansition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 33) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond . 34) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . 35) when the device is operated with input clock ji tter, this parameter needs to be derated by {? t jit.duty.max ? t err(6-10per).max } and {? t jit.duty.min ? t err(6-10per).min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps, t err(6- 10per).max = + 293 ps, t jit.duty.min = ? 106 ps and t jit.duty.max = + 94 ps, then t aof.min(derated) = t aof.min + {? t jit.duty.max ? t err(6-10per).max } = ? 450 ps + {? 94 ps ? 293 ps} = ? 837 ps and t aof.max(derated) = t aof.max + {? t jit.duty.min ? t err(6-10per).min } = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (caution on the min/max usage!) parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) 8) min. max. dq output access time from ck / ck t ac ?450 +450 ps 9) dqs output access time from ck / ck t dqsck ?400 +400 ps 9) average clock high pulse width t ch.avg 0.48 0.52 t ck.avg 10)11) average clock low pulse width t cl.avg 0.48 0.52 t ck.avg 10)11) average clock period t ck.avg 3000 8000 ps ? dq and dm input setup time t ds.base 100 ? ps 12)13)14) dq and dm input hold time t dh.base 175 ? ps 13)14)15) control & address input pulse width for each input t ipw 0.6 ? t ck.avg ? dq and dm input pulse width for each input t dipw 0.35 ? t ck.avg ? data-out high-impedance time from ck / ck t hz ? t ac.max ps 9)16) dqs/dqs low-impedance time from ck / ck t lz.dqs t ac.min t ac.max ps 9)16) dq low impedance time from ck/ck t lz.dq 2x t ac.min t ac.max ps 9)16) dqs-dq skew for dqs & associated dq signals t dqsq ? 240 ps 17) ck half pulse width t hp min ( t ch.abs , t cl.abs ) __ ps 18) dq hold skew factor t qhs ? 340 ps 19) dq/dqs output hold time from dqs t qh t hp ? t qhs ?ps 20) write command to dqs associated clock edges wl rl?1 nck ?
internet data sheet rev. 1.21, 2007-03 23 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules dqs latching rising transition to associated clock edges t dqss ? 0.25 + 0.25 t ck.avg 21) dqs input high pulse width t dqsh 0.35 ? t ck.avg ? dqs input low pulse width t dqsl 0.35 ? t ck.avg ? dqs falling edge to ck setup time t dss 0.2 ? t ck.avg 21) dqs falling edge hold time from ck t dsh 0.2 ? t ck.avg 21) write postamble t wpst 0.4 0.6 t ck.avg ? write preamble t wpre 0.35 ? t ck.avg ? address and control input setup time t ls.base 200 ? ps 22)23) address and control input hold time t lh.base 275 ? ps 23)24) read preamble t rpre 0.9 1.1 t ck.avg 25)26) read postamble t rpst 0.4 0.6 t ck.avg 25)27) active to precharge command t ras 45 70000 ns 28) active to active command period for 1kb page size products t rrd 7.5 ? ns 28) active to active command period for 2kb page size products t rrd 10 ? ns 28) four activate window for 1kb page size products t faw 37.5 ? ns 28) four activate window for 2kb page size products t faw 50 ? ns 28) cas to cas command delay t ccd 2?nck? write recovery time t wr 15 ? ns 28) auto-precharge write recovery + precharge time t dal wr + t nrp ?nck 29)30) internal write to read command delay t wtr 7.5 ? ns 28)31) internal read to precharge command delay t rtp 7.5 ? ns 28) exit self-refresh to a non-read command t xsnr t rfc +10 ? ns 28) exit self-refresh to read command t xsrd 200 ? nck ? exit precharge power-down to any valid command (other than nop or deselect) t xp 2?nck? exit power down to read command t xard 2?nck? exit active power-down mode to read command (slow exit, lower power) t xards 7 ? al ? nck ? cke minimum pulse width ( high and low pulse width) t cke 3?nck 32) odt turn-on delay t aond 22nck? odt turn-on t aon t ac.min t ac.max +0.7 ns 9)33) odt turn-on (power down mode) t aonpd t ac.min +2 2 x t ck.avg + t ac.max +1 ns ? odt turn-off delay t aofd 2.5 2.5 nck ? odt turn-off t aof t ac.min t ac.max +0.6 ns 34)35) odt turn-off (power down mode) t aofpd t ac.min + 2 2.5 x t ck.avg + t ac.max +1 ns ? parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) 8) min. max.
internet data sheet rev. 1.21, 2007-03 24 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules odt to power down entry latency t anpd 3??nck? odt to power down exit latency t axpd 8nck? mode register set command cycle time t mrd 2?nck? mrs command to odt update delay t mod 012ns 28) ocd drive mode output delay t oit 012ns 28) minimum time clocks remain on after cke asynchronously drops low t delay t ls + t ck .avg + t lh ?? ns ? 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs / rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) new units, ? t ck.avg ? and ?nck?, are introduced in ddr2?667 and ddr2?800. unit ? t ck.avg ? represents the actual t ck.avg of the input clock under operation. unit ?nck? represents one clock cycle of the i nput clock, counting the actual clock edges. note that in ddr2?4 00 and ddr2?533, ? t ck ? is used for both concepts. example: t xp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm + 2, even if (tm + 2 - tm) is 2 x t ck.avg + t err.2per(min) . 9) when the device is operated with input clock jitter, this parameter needs to be derated by the actual t err(6-10per) of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps and t err(6- 10per).max = + 293 ps, then t dqsck.min(derated) = t dqsck.min ? t err(6-10per).max = ? 400 ps ? 293 ps = ? 693 ps and t dqsck.max(derated) = t dqsck.max ? t err(6-10per).min = 400 ps + 272 ps = + 672 ps. similarly, t lz.dq for ddr2?667 derates to t lz.dq.min(derated) = - 900 ps ? 293 ps = ? 1193 ps and t lz.dq.max(derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 10) input clock jitter spec parameter. these parameters are referr ed to as 'input clock jitter s pec parameters' and these parame ters apply to ddr2?667 and ddr2?800 only. the jitter specified is a random jitter meeting a gaussian distribution. 11) these parameters are specified per their average values, howe ver it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of spec values are to be used for calculations). 12) input waveform timing t ds with differential data strobe enabled mr[bit10] = 0, is referenced from the input signal crossing at the v ih.ac level to the differential data strobe crosspoint for a ri sing signal, and from the input signal crossing at the v il.ac level to the differential data strobe crosspoint for a falling signal applied to the devic e under test. dqs, dqs signals must be monotonic between v il(dc)max and v ih(dc)min . see figure 2 . 13) if t ds or t dh is violated, data corruption may occur and the data must be re -written with valid data before a valid read can be executed. 14) these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs / dqs ) crossing. 15) input waveform timing t dh with differential data strobe enabled mr[bit10] = 0, is refe renced from the differential data strobe crosspoint to the input signal crossing at the v ih.dc level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il.dc level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il.dc.max and v ih.dc.min . see figure 2 . 16) t hz and t lz transitions occur in the same access time as valid data trans itions. these parameters are refe renced to a specific voltage lev el which specifies when the device output is no longer driving ( t hz ), or begins driving ( t lz ) . 17) t dqsq : consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of the output drivers as well as o utput slew rate mismatch between dqs / dqs and associated dq in any given cycle. 18) t hp is the minimum of the absolute half period of the actual input clock. t hp is an input parameter but not an input specification parameter. it is used in conjunction with t qhs to derive the dram output timing t qh . the value to be used for t qh calculation is determined by the following equation; t hp = min ( t ch.abs , t cl.abs ), where, t ch.abs is the minimum of the actual instantaneous clock high time; t cl.abs is the minimum of the actual in stantaneous clock low time. parameter symbol ddr2?667 unit note 1)2)3)4)5)6)7) 8) min. max.
internet data sheet rev. 1.21, 2007-03 25 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 19) t qhs accounts for: 1) the pulse duration distortion of on-ch ip clock circuits, which repr esents how well the actual t hp at the input is transferred to the output; and 2) the worst case push-out of dq s on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channe l variation of the output drivers. 20) t qh = t hp ? t qhs , where: t hp is the minimum of the absolute half period of the actual input clock; and t qhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the t qh value is; and the larger the valid data eye will be.} examples: 1) if the system provides t hp of 1315 ps into a ddr2?667 sdram, the dram provides t qh of 975 ps minimum. 2) if the system provides t hp of 1420 ps into a ddr2?667 sdram, the dram provides t qh of 1080 ps minimum. 21) these parameters are measured from a data strobe signal ((l/u/r)dqs / dqs ) crossing to its respec tive clock signal (ck / ck ) crossing. the spec values are not affected by t he amount of clock jitter applied (i.e. t jit.per , t jit.cc , etc.), as these are relative to the clock signal crossing. that is, these param eters should be met whether clock jitter is present or not. 22) input waveform timing is referenced from the input signal crossing at the v ih.ac level for a rising signal and v il.ac for a falling signal applied to the device under test. see figure 3 . 23) these parameters are measured from a command/address signal (c ke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck / ck ) crossing. the spec values are not affect ed by the amount of cl ock jitter applied (i.e. t jit.per , t jit.cc , etc.), as the setup and hold are relative to the clock signal cr ossing that latches the command/address. that is, these paramet ers should be met whether clock jitter is present or not. 24) input waveform timing is referenced from the input signal crossing at the v il.dc level for a rising signal and v ih.dc for a falling signal applied to the device under test. see figure 3 . 25) t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving ( t rpst ), or begins driving ( t rpre ). figure 1 shows a method to calculate these points when the device is no longer driving ( t rpst ), or begins driving ( t rpre ) by measuring the signal at two different voltages. the actual voltage measurement poi nts are not critical as long as the calculation is consistent. 26) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.per of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t jit.per.min = ? 72 ps and t jit.per.max = + 93 ps, then t rpre.min(derated) = t rpre.min + t jit.per.min = 0.9 x t ck.avg ? 72 ps = + 2178 ps and t rpre.max(derated) = t rpre.max + t jit.per.max = 1.1 x t ck.avg + 93 ps = + 2843 ps. (caution on the min/max usage!). 27) when the device is operated with i nput clock jitter, this parameter needs to be derated by the actual t jit.duty of the input clock. (output deratings are relative to the sdram input clock.) for ex ample, if the measured jitter into a ddr2?667 sdram has t jit.duty.min = ? 72 ps and t jit.duty.max = + 93 ps, then t rpst.min(derated) = t rpst.min + t jit.duty.min = 0.4 x t ck.avg ? 72 ps = + 928 ps and t rpst.max(derated) = t rpst.max + t jit.duty.max = 0.6 x t ck.avg + 93 ps = + 1592 ps. (caution on the min/max usage!). 28) for these parameters, the ddr2 sdram device is characterized and verified to support t nparam = ru{ t param / t ck.avg }, which is in clock cycles, assuming all input cl ock jitter specifications are satisfied. for example, the device will support t nrp = ru{ t rp / t ck.avg }, which is in clock cycles, if all input clock jitter specifications are me t. this means: for ddr2?667 5?5?5, of which t rp = 15 ns, the device will support t nrp = ru{ t rp / t ck.avg } = 5, i.e. as long as the input cloc k jitter specifications are met, prechar ge command at tm and active command at tm + 5 is valid even if (tm + 5 - tm) is less than 15 ns due to input clock jitter. 29) dal = wr + ru{ t rp (ns) / t ck (ns)}, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for t rp , if the result of the division is not already an integer, round up to the next highest integer. t ck refers to the application clock period. example: for ddr2?533 at t ck = 3.75 ns with t wr programmed to 4 clocks. t dal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 30) t dal.nck = wr [nck] + t nrp.nck = wr + ru{ t rp [ps] / t ck.avg [ps] }, where wr is the value programmed in the emr. 31) t wtr is at lease two clocks (2 x t ck ) independent of operation frequency. 32) t cke.min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level t he entire time it takes to achieve the 3 clo cks of registration. thus, after any cke tr ansition, cke may not transition from its v alid level during the time period of t is + 2 x t ck + t ih . 33) odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from t aond . 34) odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . 35) when the device is operated with input clock ji tter, this parameter needs to be derated by {? t jit.duty.max ? t err(6-10per).max } and {? t jit.duty.min ? t err(6-10per).min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2?667 sdram has t err(6-10per).min = ? 272 ps, t err(6- 10per).max = + 293 ps, t jit.duty.min = ? 106 ps and t jit.duty.max = + 94 ps, then t aof.min(derated) = t aof.min + {? t jit.duty.max ? t err(6-10per).max } = ? 450 ps + {? 94 ps ? 293 ps} = ? 837 ps and t aof.max(derated) = t aof.max + {? t jit.duty.min ? t err(6-10per).min } = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (caution on the min/max usage!)
internet data sheet rev. 1.21, 2007-03 26 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules figure 2 method for calculating transitions and endpoint figure 3 differential input waveform timing - t ds and t ds figure 4 differential input waveform timing - t ls and t lh w+= w53 6 7 hq gsr l q w 7 7 92 +[p 9 92 +[p 9 92 / [p 9 92 / [p 9 w/= w5 35( ehj l q srlqw 7 7 977 [p9 977 [p9 977 [ p9 977 [p9 w/= w53 5 ( ehjl qsrl qw 7 7 w+=w53 6 7 hq gsrl qw 7 7 w' 6 9 '' 4 9 ,+d f pl q 9 ,+g f pl q 9 5()gf 9 ,/ g f pd [ 9 ,/ d f pd [ 9 66 '4 6 '46 w'+ w'6 w'+ w,6 9 '' 4 9 ,+ d f plq 9 ,+ g f plq 9 5()gf 9 ,/ g f pd [ 9 ,/ d f pd [ 9 66 &. &. w, + w, 6 w, +
internet data sheet rev. 1.21, 2007-03 27 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 18 timing parameter by speed grade - ddr2?533 parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?500 +500 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)18) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?ns 9) dq and dm input hold time (differential data strobe) t dh (base) 225 ? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?450 + 450 ps ? dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck ? dqs-dq skew (for dqs & associated dq signals) t dqsq ? 300 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setup time (differential data strobe) t ds (base) 100 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck ? four activate window period t faw 37.5 ? ns ? 50 ? ns 13) clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 375 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck ? address and control input setup time t is (base) 250 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hp ? t qhs ???
internet data sheet rev. 1.21, 2007-03 28 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules data hold skew factor t qhs ? 400 ps ? average periodic refresh interval t refi ?7.8 s 14)15) ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns? precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns? read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.25 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns ? write recovery time for write with auto- precharge wr t wr / t ck t ck 20) internal write to read command delay t wtr 7.5 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-c hannel to n-channel variation of t he output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the act ual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). parameter symbol ddr2?533 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.21, 2007-03 29 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 19 timing parameter by speed grade - ddr2-400 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 3 ?ordering information for rohs compliant products? on page 5 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active pow er-down modes for additional power saving vi a mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max. dq output access time from ck / ck t ac ?600 +600 ps ? cas a to cas b command period t ccd 2? t ck ? ck, ck high-level width t ch 0.45 0.55 t ck ? cke minimum high and low pulse width t cke 3? t ck ? ck, ck low-level width t cl 0.45 0.55 t ck ? auto-precharge write recovery + precharge time t dal wr + t rp ? t ck 8)22) minimum time clocks remain on after cke asynchronously drops low t delay t is + t ck + t ih ?? ns 9) dq and dm input hold time (differential data strobe) t dh (base) 275 ?? ps 10) dq and dm input hold time (single ended data strobe) t dh1 (base) ?25 ? ps 11) dq and dm input pulse width (each input) t dipw 0.35 ? t ck ? dqs output access time from ck / ck t dqsck ?500 + 500 ps ? dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? t ck ? dqs-dq skew (for dqs & associated dq signals) t dqsq ? 350 ps 11) write command to 1st dqs latching transition t dqss ? 0.25 + 0.25 t ck ? dq and dm input setup time (differential data strobe) t ds (base) 150 ? ps 11) dq and dm input setup time (single ended data strobe) t ds1 (base) ?25 ? ps 11)
internet data sheet rev. 1.21, 2007-03 30 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? t ck ? dqs falling edge to ck setup time (write cycle) t dss 0.2 ? t ck ? four activate window period t faw 37.5 ? ns ? 50 ? ns 13) clock half period t hp min. ( t cl, t ch ) 12) data-out high-impedance time from ck / ck t hz ? t ac.max ps 13) address and control input hold time t ih (base) 475 ? ps 11) address and control input pulse width (each input) t ipw 0.6 ? t ck ? address and control input setup time t is (base) 350 ? ps 11) dq low-impedance time from ck / ck t lz(dq) 2 t ac.min t ac.max ps 14) dqs low-impedance from ck / ck t lz(dqs) t ac.min t ac.max ps 14) mode register set command cycle time t mrd 2? t ck ? ocd drive mode output delay t oit 012ns? data output hold time from dqs t qh t hp ? t qhs ??? data hold skew factor t qhs ? 450 ps ? average periodic refresh interval t refi ?7.8 s 14)15) ?3.9 s 16)18) auto-refresh to active/auto-refresh command period t rfc 75 ? ns 17) precharge-all (4 banks) command period t rp t rp +1 t ck ?ns? precharge-all (8 banks) command period t rp 15 + 1 t ck ?ns? read preamble t rpre 0.9 1.1 t ck 14) read postamble t rpst 0.40 0.60 t ck 14) active bank a to active bank b command period t rrd 7.5 ? ns 14)18) 10 ? ns 16)20) internal read to precharge command delay t rtp 7.5 ? ns ? write preamble t wpre 0.25 x t ck ? t ck ? write postamble t wpst 0.40 0.60 t ck 19) write recovery time for write without auto- precharge t wr 15 ? ns ? write recovery time for write with auto- precharge wr t wr / t ck t ck 20) internal write to read command delay t wtr 10 ? ns 21) exit power down to any valid command (other than nop or deselect) t xard 2? t ck 22) exit active power-down mode to read command (slow exit, lower power) t xards 6 ? al ? t ck 22) exit precharge power-down to any valid command (other than nop or deselect) t xp 2? t ck ? parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.21, 2007-03 31 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules exit self-refresh to non-read command t xsnr t rfc +10 ? ns ? exit self-refresh to read command t xsrd 200 ? t ck ? 1) for details and notes see the relevant qimonda component data sheet 2) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v. see notes 5)6)7)8) 3) timing that is not specified is ille gal and after such an event, in order to guarantee proper operation, the dram must be pow ered down and then restarted through the specified initializa tion sequence before normal operation can continue. 4) timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. for dqs si gnals timings are guaranteed with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. 5) the ck / ck input reference level (for timing reference to ck / ck ) is the point at which ck and ck cross. the dqs / dqs , rdqs/ rdqs , input reference level is the crosspoint when in differential strobe mode. 6) inputs are not recognized as valid until v ref stabilizes. during the period before v ref stabilizes, cke = 0.2 x v ddq is recognized as low. 7) the output timing reference voltage level is v tt . 8) for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mr. 9) the clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) for timing definition, refer to the component data sheet. 11) consists of data pin skew and output pattern effects, and p-channel to n-channel variation of t he output drivers as well as output slew rate mis-match between dqs / dqs and associated dq in any given cycle. 12) min ( t cl , t ch ) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch ). 13) the t hz , t rpst and t lz , t rpre parameters are referenced to a specific voltage level, which specify when the device output is no longer driving ( t hz, t rpst ), or begins driving ( t lz, t rpre ). t hz and t lz transitions occur in the same access time windows as valid da ta transitions.these parameters are verified by design and characteri zation, but not subject to production test. 14) the auto-refresh command interval has be reduced to 3.9 s when operating the ddr2 dram in a temperature range between 85 c and 95 c. 15) 0 c t case 85 c 16) 85 c < t case 95 c 17) a maximum of eight auto-refresh commands can be posted to any given ddr2 sdram device. 18) the t rrd timing parameter depends on the page size of the dram organization. see table 3 ?ordering information for rohs compliant products? on page 5 . 19) the maximum limit for the t wpst parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) wr must be programmed to fulfill the minimum requirement for the t wr timing parameter, where wr min [cycles] = t wr (ns)/ t ck (ns) rounded up to the next integer value. t dal = wr + ( t rp / t ck ). for each of the terms, if not already an integer, round to the next highest integer. t ck refers to the application clock period. wr refers to the wr parameter stored in the mrs. 21) minimum t wtr is two clocks when operating the ddr2-sdram at frequencies 200 ? z. 22) user can choose two different active power-down modes for addi tional power saving via mrs address bit a12. in ?standard acti ve power- down mode? (mr, a12 = ?0?) a fast power-down exit timing t xard can be used. in ?low active power-down mode? (mr, a12 =?1?) a slow power-down exit timing t xards has to be satisfied. parameter symbol ddr2?400 unit note 1)2)3)4)5) 6)7) min. max.
internet data sheet rev. 1.21, 2007-03 32 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3.3.3 odt ac electrical characteristics this chapter contains the odt ac electrical characteristics tables. table 20 odt ac characteristics and operating conditions for ddr2-667 & ddr2-800 table 21 odt ac characteristics and operating conditions for ddr2-533/ddr2-400 symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck ? t aon odt turn-on t ac.min t ac.max + 0.7 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns ? t aofd odt turn-off delay 2.5 2.5 t ck ? t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns ? t anpd odt to power down mode entry latency 3 ? t ck ? t axpd odt power down exit latency 8 ? t ck ? symbol parameter / condition values unit note min. max. t aond odt turn-on delay 2 2 t ck ? t aon odt turn-on t ac.min t ac.max + 1 ns ns 1) 1) odt turn on time min. is when the devic e leaves high impedance and odt re sistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond . t aonpd odt turn-on (power-down modes) t ac.min + 2 ns 2 t ck + t ac.max + 1 ns ns ? t aofd odt turn-off delay 2.5 2.5 t ck ? t aof odt turn-off t ac.min t ac.max + 0.6 ns ns 2) 2) odt turn off time min. is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from t aofd . t aofpd odt turn-off (power-down modes) t ac.min + 2 ns 2.5 t ck + t ac.max + 1 ns ns ? t anpd odt to power down mode entry latency 3 ? t ck ? t axpd odt power down exit latency 8 ? t ck ?
internet data sheet rev. 1.21, 2007-03 33 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 3.4 i dd specifications and conditions this chapter describes the i dd specifications and conditions. table 22 i dd measurement conditions parameter symbol note 1)2) 3)4)5)6) operating current 0 one bank active - precharge; t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ck.min , t rc = t rc.min , t ras = t ras.min , t rcd = t rcd.min , al = 0, cl = cl .min ; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are switching, data bus inputs are switching i dd2n precharge power-down current other control and address inputs are st able, data bus inputs are floating . i dd2p precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ck.min ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to low (fast power-down exit); i dd3p(0) active power-down current all banks open; t ck = t ck.min , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to high (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.min ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min ; t ck = t ck.min ; t ras = t ras.max. , t rp = t rp.max ; cke is high, cs is high between valid commands. address inputs are switching; data bus in puts are switching; i dd4w burst refresh current t ck = t ck.min ., refresh command every t rfc = t rfc.min interval, cke is high, cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ck.min , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs ar e switching, data bus inputs are switching. i dd5d
internet data sheet rev. 1.21, 2007-03 34 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 23 definitions for i dd self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. reset is low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) definitions for i dd see table 23 3) for two rank modules: for all active current meas urements the other rank is in precharge power-down mode i dd2p 4) reset signal is high for all currents, except for i dd6 (self refresh) 5) all current measurements includes r egister and pll current consumption 6) for details and notes see the relevant qimonda component data sheet parameter description low v in v il(ac).max , high is defined as v in v ih(ac).min stable inputs are stable at a high or low level floating inputs are v ref = v ddq /2 switching inputs are changing between high and low every ot her clock (once per 2 cycles) for address and control signals, and inputs changing between high and low every other data transfer (once per cycle) for dq signals not including mask or strobes. parameter symbol note 1)2) 3)4)5)6)
internet data sheet rev. 1.21, 2007-03 35 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 24 i dd specification hys72t[32000/64001/64020]hr?2.5?a product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a unit note 1) 1) module i dd is calculated on the basis of component i dd and currents includes registers and pll. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 72 72 72 1 rank 1 rank 2 ranks ?2.5 ?2.5 ?2.5 symbol max. max. max. i dd0 1110 1780 1150 ma 2) 2) the other rank is in i dd2p precharge power-down standby current mode i dd1 1200 1960 1240 ma 2) i dd2n 880 1330 1330 ma 3) 3) both ranks are in the same i dd mode i dd2p 480 520 520 ma 3) i dd2q 750 1060 1060 ma 3) i dd3n 880 1330 1330 ma 3) i dd3p(mrs= 0) 630 830 830 ma 3) i dd3p(mrs= 1) 480 520 520 ma 3) i dd4r 1560 2680 1600 ma 2) i dd4w 1650 2860 1690 ma 2) i dd5b 1290 2140 1330 ma 2) i dd5d 480 540 540 ma 3)4) 4) values for 0 c < t case 85 c i dd6 35 70 70 ma 3)4) i dd7 1830 3220 1870 ma 2)
internet data sheet rev. 1.21, 2007-03 36 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 25 i dd specification hys72t[32000/64001/64020]hr?3?a product type hys72t32000hr?3?a HYS72T64001HR?3?a hys72t64020hr?3?a unit note 1) 1) module i dd is calculated on the basis of component i dd and currents includes registers and pll. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 72 72 72 1 rank 1 rank 2 ranks ?3 ?3 ?3 symbol max. max. max. i dd0 970 1770 1010 ma 2) 2) the other rank is in i dd2p precharge power-down standby current mode i dd1 1060 1950 1100 ma 2) i dd2n 790 1410 1200 ma 3) 3) both ranks are in the same i dd mode i dd2p 430 680 470 ma 3) i dd2q 660 1140 930 ma 3) i dd3n 790 1410 1200 ma 3) i dd3p(mrs= 0) 560 940 730 ma 3) i dd3p(mrs= 1) 430 690 480 ma 3) i dd4r 1380 2580 1420 ma 2) i dd4w 1420 2670 1460 ma 2) i dd5b 1240 2310 1280 ma 2) i dd5d 440 700 490 ma 3)4) 4) values for 0 c t case 85 c i dd6 35 70 70 ma 3)4) i dd7 1690 3210 1730 ma 2)
internet data sheet rev. 1.21, 2007-03 37 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 26 i dd specification hys72t[32000/64001/64020]hr?3s?a product type hys72t32000hr?3s?a HYS72T64001HR?3s?a hys72t64020hr?3s?a unit note 1) 1) module i dd is calculated on the basis of component i dd and currents includes registers and pll. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 72 72 72 1 rank 1 rank 2 ranks ?3s ?3s ?3s symbol max. max. max. i dd0 940 1710 980 ma 2) 2) the other rank is in i dd2p precharge power-down standby current mode i dd1 1020 1870 1060 ma 2) i dd2n 790 1410 1200 ma 3) 3) both ranks are in the same i dd mode i dd2p 430 680 470 ma 3) i dd2q 660 1140 930 ma 3) i dd3n 790 1410 1200 ma 3) i dd3p(mrs= 0) 560 940 730 ma 3) i dd3p(mrs= 1) 430 690 480 ma 3) i dd4r 1380 2580 1420 ma 2) i dd4w 1420 2670 1460 ma 2) i dd5b 1240 2310 1280 ma 2) i dd5d 440 700 490 ma 3)4) 4) values for 0 c t case 85 c i dd6 35 70 70 ma 3)4) i dd7 1630 3080 1670 ma 2)
internet data sheet rev. 1.21, 2007-03 38 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 27 i dd specification for hys72t[32000/64001/64020]hr?3.7?a product type hys72t32000hr?3.7?a HYS72T64001HR?3.7?a hys72t64020hr?3.7?a unit note 1) 1) module i dd is calculated on the basis of component i dd and currents includes registers and pll. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 72 72 72 1 rank 1 rank 2 ranks ?3.7 ?3.7 ?3.7 symbol max. max. max. i dd0 830 1490 860 ma 2) 2) the other rank is in i dd2p precharge power-down standby current mode i dd1 870 1580 910 ma 2) i dd2n 650 1130 960 ma 3) 3) both ranks are in the same i dd mode i dd2p 370 570 400 ma 3) i dd2q 560 950 780 ma 3) i dd3n 650 1130 960 ma 3) i dd3p(mrs= 0) 470 790 620 ma 3) i dd3p(mrs= 1) 370 570 400 ma 3) i dd4r 1140 2120 1180 ma 2) i dd4w 1190 2210 1220 ma 2) i dd5b 1140 2120 1180 ma 2) i dd5d 380 610 440 ma 3)4) 4) values for 0 c t case 85 c i dd6 35 70 70 ma 3)4) i dd7 1550 2930 1580 ma 2)
internet data sheet rev. 1.21, 2007-03 39 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 28 i dd specification for hys72t[32000/64001/64020]hr-5-a product type hys72t32000hr?5?a HYS72T64001HR?5?a hys72t64020hr?5?a unit note 1) 1) module i dd is calculated on the basis of component i dd and currents includes registers and pll. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled. organization 256mb 512mb 512mb 72 72 72 1 rank 1 rank 2 ranks ?5 ?5 ?5 symbol max. max. max. i dd0 730 1310 760 ma 2) 2) the other rank is in i dd2p precharge power-down standby current mode i dd1 770 1400 810 ma 2) i dd2n 530 910 780 ma 3) 3) both ranks are in the same i dd mode i dd2p 310 480 350 ma 3) i dd2q 460 770 640 ma 3) i dd3n 550 950 820 ma 3) i dd3p(mrs= 0) 390 640 510 ma 3) i dd3p(mrs= 1) 310 480 350 ma 3) i dd4r 910 1670 940 ma 2) i dd4w 950 1760 990 ma 2) i dd5b 1040 1940 1080 ma 2) i dd5d 330 510 380 ma 3)4) 4) values for 0 c t case 85 c i dd6 35 70 70 ma 3)4) i dd7 1400 2660 1440 ma 2)
internet data sheet rev. 1.21, 2007-03 40 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 4 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 29 ?spd codes for pc2?6400r?666? on page 40 ? table 30 ?spd codes for pc2?5300r?444? on page 45 ? table 31 ?spd codes for pc2?5300r?555? on page 49 ? table 32 ?spd codes for pc2?4200r?444? on page 53 ? table 33 ?spd codes for pc2?3200r?333? on page 57 table 29 spd codes for pc2?6400r?666 product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?6400r?666 pc2?6400r?666 pc2?6400r?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 25 25 25 10 t ac sdram @ cl max (byte 18) [ns] 40 40 40 11 error correction support (non-ecc, ecc) 02 02 02
internet data sheet rev. 1.21, 2007-03 41 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 70 70 70 19 dimm mechanical characteristics 01 01 01 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45 25 t ck @ cl max -2 (byte 18) [ns] 3d 3d 3d 26 t ac sdram @ cl max -2 [ns] 50 50 50 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 40 32 t as.min and t cs.min [ns] 17 17 17 33 t ah.min and t ch.min [ns] 25 25 25 34 t ds.min [ns] 05 05 05 35 t dh.min [ns] 12 12 12 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?6400r?666 pc2?6400r?666 pc2?6400r?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 42 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 14 14 14 45 t qhs.max [ns] 1e 1e 1e 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 535353 48 psi(t-a) dram 82 82 82 49 ? t 0 (dt0) 5b5b5b 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 2b 2b 2b 51 ? t 2p (dt2p) 29 29 29 52 ? t 3n (dt3n) 29 29 29 53 ? t 3p.fast (dt3p fast) 363636 54 ? t 3p.slow (dt3p slow) 191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 4e 4e 4e 56 ? t 5b (dt5b) 17 17 17 57 ? t 7 (dt7) 262626 58psi(ca) pll c4c4c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 70 70 70 61 ? t reg (dtreg) / toggle rate b0 b0 b0 62 spd revision 12 12 12 63 checksum of bytes 0-62 f7 31 f9 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?6400r?666 pc2?6400r?666 pc2?6400r?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 43 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 79 product type, char 7 30 30 32 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 52 52 52 83 product type, char 11 32 32 32 84 product type, char 12 2e 2e 2e 85 product type, char 13 35 35 35 86 product type, char 14 41 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 3x 3x 3x 92 test program revision code xx xx xx product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?6400r?666 pc2?6400r?666 pc2?6400r?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 44 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys72t32000hr?2.5?a HYS72T64001HR?2.5?a hys72t64020hr?2.5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?6400r?666 pc2?6400r?666 pc2?6400r?666 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 45 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 30 spd codes for pc2?5300r?444 product type hys72t32000hr?3?a HYS72T64001HR?3?a hys72t64020hr?3?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?444 pc2?5300r?444 pc2?5300r?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 01 01 01 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 30 30 30 24 t ac sdram @ cl max -1 [ns] 45 45 45
internet data sheet rev. 1.21, 2007-03 46 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 30 30 30 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 30 30 30 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 40 32 t as.min and t cs.min [ns] 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 17 17 17 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 39 39 39 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 18 18 18 45 t qhs.max [ns] 22 22 22 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 525252 48 psi(t-a) dram 82 82 82 49 ? t 0 (dt0) 474747 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 25 25 25 51 ? t 2p (dt2p) 29 29 29 product type hys72t32000hr?3?a HYS72T64001HR?3?a hys72t64020hr?3?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?444 pc2?5300r?444 pc2?5300r?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 47 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 52 ? t 3n (dt3n) 25 25 25 53 ? t 3p.fast (dt3p fast) 2f2f2f 54 ? t 3p.slow (dt3p slow) 191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 44 44 44 56 ? t 5b (dt5b) 17 17 17 57 ? t 7 (dt7) 242424 58psi(ca) pll c4c4c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 68 68 68 61 ? t reg (dtreg) / toggle rate 94 94 94 62 spd revision 12 12 12 63 checksum of bytes 0-62 a4 de a6 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 product type hys72t32000hr?3?a HYS72T64001HR?3?a hys72t64020hr?3?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?444 pc2?5300r?444 pc2?5300r?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 48 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 79 product type, char 7 30 30 32 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 52 52 52 83 product type, char 11 33 33 33 84 product type, char 12 41 41 41 85 product type, char 13 20 20 20 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 6x 6x 6x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys72t32000hr?3?a HYS72T64001HR?3?a hys72t64020hr?3?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?444 pc2?5300r?444 pc2?5300r?444 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 49 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 31 spd codes for pc2?5300r?555 product type hys72t32000hr?3s?a HYS72T64001HR?3s?a hys72t64020hr?3s?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?555 pc2?5300r?555 pc2?5300r?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 30 30 30 10 t ac sdram @ cl max (byte 18) [ns] 45 45 45 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 01 01 01 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 03 03 03 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d
internet data sheet rev. 1.21, 2007-03 50 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 40 32 t as.min and t cs.min [ns] 20 20 20 33 t ah.min and t ch.min [ns] 27 27 27 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 17 17 17 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 18 18 18 45 t qhs.max [ns] 22 22 22 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 525252 48 psi(t-a) dram 82 82 82 49 ? t 0 (dt0) 434343 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 25 25 25 product type hys72t32000hr?3s?a HYS72T64001HR?3s?a hys72t64020hr?3s?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?555 pc2?5300r?555 pc2?5300r?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 51 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 51 ? t 2p (dt2p) 29 29 29 52 ? t 3n (dt3n) 25 25 25 53 ? t 3p.fast (dt3p fast) 2f2f2f 54 ? t 3p.slow (dt3p slow) 191919 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 44 44 44 56 ? t 5b (dt5b) 17 17 17 57 ? t 7 (dt7) 222222 58psi(ca) pll c4c4c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 68 68 68 61 ? t reg (dtreg) / toggle rate 94 94 94 62 spd revision 12 12 12 63 checksum of bytes 0-62 d1 0b d3 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 product type hys72t32000hr?3s?a HYS72T64001HR?3s?a hys72t64020hr?3s?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?555 pc2?5300r?555 pc2?5300r?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 52 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 78 product type, char 6 30 30 30 79 product type, char 7 30 30 32 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 52 52 52 83 product type, char 11 33 33 33 84 product type, char 12 53 53 53 85 product type, char 13 41 41 41 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 3x 3x 3x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys72t32000hr?3s?a HYS72T64001HR?3s?a hys72t64020hr?3s?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?5300r?555 pc2?5300r?555 pc2?5300r?555 jedec spd revision rev. 1.2 rev. 1.2 rev. 1.2 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 53 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 32 spd codes for pc2?4200r?444 product type hys72t32000hr?3.7?a HYS72T64001HR?3.7?a hys72t64020hr?3.7?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r?444 pc2?4200r?444 pc2?4200r?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 00 00 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d
internet data sheet rev. 1.21, 2007-03 54 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 40 32 t as.min and t cs.min [ns] 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 22 22 22 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 45 t qhs.max [ns] 28 28 28 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 555555 48 psi(t-a) dram 82 82 82 49 ? t 0 (dt0) 373737 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 1f 1f 1f product type hys72t32000hr?3.7?a HYS72T64001HR?3.7?a hys72t64020hr?3.7?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r?444 pc2?4200r?444 pc2?4200r?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 55 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 51 ? t 2p (dt2p) 21 21 21 52 ? t 3n (dt3n) 1d 1d 1d 53 ? t 3p.fast (dt3p fast) 282828 54 ? t 3p.slow (dt3p slow) 141414 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 2c 2c 2c 56 ? t 5b (dt5b) 15 15 15 57 ? t 7 (dt7) 212121 58psi(ca) pll c4c4c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 61 61 61 61 ? t reg (dtreg) / toggle rate 78 78 78 62 spd revision 11 11 11 63 checksum of bytes 0-62 a8 e2 aa 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 product type hys72t32000hr?3.7?a HYS72T64001HR?3.7?a hys72t64020hr?3.7?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r?444 pc2?4200r?444 pc2?4200r?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 56 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 78 product type, char 6 30 30 30 79 product type, char 7 30 30 32 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 52 52 52 83 product type, char 11 33 33 33 84 product type, char 12 2e 2e 2e 85 product type, char 13 37 37 37 86 product type, char 14 41 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 4x 4x 4x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys72t32000hr?3.7?a HYS72T64001HR?3.7?a hys72t64020hr?3.7?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?4200r?444 pc2?4200r?444 pc2?4200r?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 57 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 33 spd codes for pc2?3200r?333 product type hys72t32000hr?5?a HYS72T64001HR?5?a hys72t64020hr?5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r?333 pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0d 0d 4 number of column addresses 0a 0b 0a 5 dimm rank and stacking information 60 60 61 6 data width 48 48 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 11 error correction support (non-ecc, ecc) 02 02 02 12 refresh rate and type 82 82 82 13 primary sdram width 08 04 08 14 error checking sdram width 08 04 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 dimm mechanical characteristics 00 00 00 20 dimm type information 01 01 01 21 dimm attributes 04 05 05 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60
internet data sheet rev. 1.21, 2007-03 58 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 1e 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 28 28 28 31 module density per rank 40 80 40 32 t as.min and t cs.min [ns] 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 34 t ds.min [ns] 15 15 15 35 t dh.min [ns] 27 27 27 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 28 28 28 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 000000 41 t rc.min [ns] 37 37 37 42 t rfc.min [ns] 4b 4b 4b 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 23 23 23 45 t qhs.max [ns] 2d 2d 2d 46 pll relock time 0f 0f 0f 47 t case.max delta / ? t 4r4w delta 535353 48 psi(t-a) dram 82 82 82 49 ? t 0 (dt0) 2f2f2f 50 ? t 2n (dt2n, udimm) or ? t 2q (dt2q, rdimm) 19 19 19 51 ? t 2p (dt2p) 21 21 21 product type hys72t32000hr?5?a HYS72T64001HR?5?a hys72t64020hr?5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r?333 pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 59 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 52 ? t 3n (dt3n) 19 19 19 53 ? t 3p.fast (dt3p fast) 202020 54 ? t 3p.slow (dt3p slow) 141414 55 ? t 4r (dt4r) / ? t 4r4w sign (dt4r4w) 26 26 26 56 ? t 5b (dt5b) 14 14 14 57 ? t 7 (dt7) 1f1f1f 58psi(ca) pll c4c4c4 59 psi(ca) reg 8c 8c 8c 60 ? t pll (dtpll) 59 59 59 61 ? t reg (dtreg) / toggle rate 5c 5c 5c 62 spd revision 11 11 11 63 checksum of bytes 0-62 d9 13 db 64 manufacturer?s jedec id code (1) 7f 7f 7f 65 manufacturer?s jedec id code (2) 7f 7f 7f 66 manufacturer?s jedec id code (3) 7f 7f 7f 67 manufacturer?s jedec id code (4) 7f 7f 7f 68 manufacturer?s jedec id code (5) 7f 7f 7f 69 manufacturer?s jedec id code (6) 51 51 51 70 manufacturer?s jedec id code (7) 00 00 00 71 manufacturer?s jedec id code (8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 37 37 37 74 product type, char 2 32 32 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 product type hys72t32000hr?5?a HYS72T64001HR?5?a hys72t64020hr?5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r?333 pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 60 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 79 product type, char 7 30 30 32 80 product type, char 8 30 31 30 81 product type, char 9 48 48 48 82 product type, char 10 52 52 52 83 product type, char 11 35 35 35 84 product type, char 12 41 41 41 85 product type, char 13 20 20 20 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 4x 4x 4x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 - 98 module serial number xx xx xx 99 - 127 not used 00 00 00 128 - 255 blank for customer use ff ff ff product type hys72t32000hr?5?a HYS72T64001HR?5?a hys72t64020hr?5?a organization 256mb 512mb 512mb 72 72 72 1 rank ( 8) 1 rank ( 4) 2 ranks ( 8) label code pc2?3200r?333 pc2?3200r?333 pc2?3200r?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
internet data sheet rev. 1.21, 2007-03 61 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 5 package outlines this chapter contains the package outlines of the products. figure 5 package outline raw card a l-dim-240-11 * /' % & $ & ? 0 $; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [
internet data sheet rev. 1.21, 2007-03 62 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules figure 6 package outline raw card b-g l-dim-240-12 * /' % & $ & ? 0 $; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [
internet data sheet rev. 1.21, 2007-03 63 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules figure 7 package outline raw card c l-dim-240-13 * /' % & $ & ? 0 $; % ? % x u u p d [ d o o r z h g ? $ % & ' h w d l o r i f r q w d f w v ? $ ? [
internet data sheet rev. 1.21, 2007-03 64 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 6 product type nomenclature qimonda?s nomenclature uses simple coding combined with some propriatory coding. table 34 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 35 and for components in table 36 . table 34 nomenclature fields and examples table 35 ddr2 dimm nomenclature example for field number 1234567891011 micro-dimm hys 64 t 64 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512 16 0 a c ?5 ? field description values coding 1 qimonda modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 512 4 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type d so- d imm m m icro-dimm r r egistered u u nbuffered f f ully buffered
internet data sheet rev. 1.21, 2007-03 65 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules table 36 ddr2 dram nomenclature 10 speed grade ?2.5 pc2?6400 6?6?6 ?3 pc2?5300 4?4?4 ?3s pc2?5300 5?5?5 ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second 1) multiplying ?memory density per i/o? with ?module data width? and dividing by 8 for non-ecc and 9 for ecc modules gives the o verall module memory density in mbytes as listed in column ?coding?. field description values coding 1 qimonda component prefix hyb constant 2 interface voltage [v] 18 sstl_18 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?2.5 ddr2-800 6-6-6 ?3 ddr2-667 4-4-4 ?3s ddr2-667 5-5-5 ?3.7 ddr2-533 4-4-4 ?5 ddr2-400 3-3-3 field description values coding
internet data sheet rev. 1.21, 2007-03 66 09152006-j5fk-c565 hys72t[32/64]0xxhr?[2.5/3/3s/3.7/5]?a registered ddr2 sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 speed grades definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 ac timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 odt ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table of contents
edition 2007-03 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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